Assign Statement In Verilog

When describing a combinational circuit using an “always” block, we should list all of the inputs in the sensitivity list.

The condition checked within this “if” statement is defined using the Verilog bitwise OR operator.

The following example shows the use of a nested structure to describe a priority encoder.

Use the Verilog “if” statement to describe a 4-to-2 priority encoder with the truth table below: The following code is a Verilog description for this priority encoder: 1 module Prio_4_to_2( 2 input wire [3:0] x, 3 output reg [1:0] y, 4 output reg v 5 ); 6 always @* 7 if (x[3] == 1'b1) 8 y = 2'b11; 9 else if (x[2] == 1'b1) 10 y = 2'b10; 11 else if (x[1] == 1'b1) 12 y = 2'b01; 13 else 14 y = 2'b00; 15 always @* 16 if (x[3] | x[2] | x[1] | x[0]) 17 v = 1'b1; 18 else 19 v = 1'b0; 20 endmodule Line 6 introduces a useful Verilog notation.

The input with the highest priority (x[3]) is checked first.

If it’s logic high, the condition is evaluated as true and the output is set to 11.

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